After
yesterday's Compressive Sensing Hardware, let us look at the recent hardware needed to speed up Deep Learning algorithms where convolutions are a bottelneck. The last paper is also a welcome addition to people wondering about the link between architectures based on DL and those based on computer vision features. Enjoy !
YodaNN: An Architecture for Ultra-Low Power Binary-Weight CNN Acceleration by
Renzo Andri,
Lukas Cavigelli,
Davide Rossi,
Luca Benini
Convolutional neural networks (CNNs) have revolutionized the world of
computer vision over the last few years, pushing image classification beyond
human accuracy. The computational effort of today's CNNs requires power-hungry
parallel processors or GP-GPUs. Recent developments in CNN accelerators for
system-on-chip integration have reduced energy consumption significantly.
Unfortunately, even these highly optimized devices are above the power envelope
imposed by mobile and deeply embedded applications and face hard limitations
caused by CNN weight I/O and storage. This prevents the adoption of CNNs in
future ultra-low power Internet of Things end-nodes for near-sensor analytics.
Recent algorithmic and theoretical advancements enable competitive
classification accuracy even when limiting CNNs to binary (+1/-1) weights
during training. These new findings bring major optimization opportunities in
the arithmetic core by removing the need for expensive multiplications, as well
as reducing I/O bandwidth and storage. In this work, we present an accelerator
optimized for binary-weight CNNs that achieves 1510 GOp/s at 1.2 V on a core
area of only 1.33 MGE (Million Gate Equivalent) or 0.19 mm
2
and with a power
dissipation of 895 {\mu}W in UMC 65 nm technology at 0.6 V. Our accelerator
significantly outperforms the state-of-the-art in terms of energy and area
efficiency achieving 61.2 TOp/s/W@0.6 V and 1135 GOp/s/MGE@1.2 V, respectively.
Paul A. Merollaa,
John V. Arthura,
Andrew S. Cassidya,
Rathinakumar Appuswamya,
Alexander Andreopoulosa,
David J. Berga,
Jeffrey L. McKinstrya,
Timothy Melanoa,
Davis R. Barcha,
Carmelo di Nolfoa,
Pallab Dattaa,
Arnon Amira,
Brian Tabaa,
Myron D. Flicknera, and
Dharmendra S. Modhaa
Deep networks are now able to achieve human-level performance on a broad
spectrum of recognition tasks. Independently, neuromorphic
computing has now demonstrated
unprecedented energy-efficiency through a new chip architecture based on
spiking neurons, low
precision synapses, and a scalable
communication network. Here, we demonstrate that neuromorphic computing,
despite its novel
architectural primitives, can implement
deep convolution networks that (i) approach state-of-the-art classification accuracy across eight standard datasets encompassing vision and speech, (ii)
perform inference while preserving the hardware’s underlying
energy-efficiency and high throughput, running on the aforementioned
datasets at between 1,200 and 2,600
frames/s and using between 25 and 275 mW (effectively superior to 6,000 frames/s
per Watt), and (iii) can be specified and trained using
backpropagation with the same ease-of-use as contemporary deep learning.
This approach
allows the algorithmic power of deep
learning to be merged with the efficiency of neuromorphic processors,
bringing the promise
of embedded, intelligent, brain-inspired
computing one step closer.
FPGA-based hardware accelerators for convolutional neural networks (CNNs) have obtained great attentions due to their higher energy efficiency than GPUs. However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU counterparts. In this paper, we demonstrate that FPGA acceleration can be a superior solution in terms of both throughput and energy efficiency when a CNN is trained with binary constraints on weights and activations. Specifically, we propose an optimized accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages. Experiment results show that the proposed architecture is 8.3x faster and 75x more energy-efficient than a Titan X GPU for processing online individual requests (in small batch size). For processing static data (in large batch size), the proposed solution is on a par with a Titan X GPU in terms of throughput while delivering 9.5x higher energy efficiency.
Towards Closing the Energy Gap Between HOG and CNN Features for Embedded Vision by
Amr Suleiman,
Yu-Hsin Chen,
Joel Emer,
Vivienne Sze
Computer vision enables a wide range of applications in robotics/drones,
self-driving cars, smart Internet of Things, and portable/wearable electronics.
For many of these applications, local embedded processing is preferred due to
privacy and/or latency concerns. Accordingly, energy-efficient embedded vision
hardware delivering real-time and robust performance is crucial. While deep
learning is gaining popularity in several computer vision algorithms, a
significant energy consumption difference exists compared to traditional
hand-crafted approaches. In this paper, we provide an in-depth analysis of the
computation, energy and accuracy trade-offs between learned features such as
deep Convolutional Neural Networks (CNN) and hand-crafted features such as
Histogram of Oriented Gradients (HOG). This analysis is supported by
measurements from two chips that implement these algorithms. Our goal is to
understand the source of the energy discrepancy between the two approaches and
to provide insight about the potential areas where CNNs can be improved and
eventually approach the energy-efficiency of HOG while maintaining its
outstanding performance accuracy.
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