There won't be a #NIPS2016 workshop on "Mapping Machine Learning to Hardware"

If you are coming to NIPS in Barcelona there won't be a "Mapping Machine Learning to Hardware" workshop. We tried but our proposal did not get accepted. 

As a reminder, this was our proposal.

Speakers line-up

• Yoshua Bengio, University of Montreal 
• Ashok Veeraraghavan, Rice University, 
• Bill Dally, Stanford University and NVIDIA, 
• Julien Demouth, NVIDIA 
• Eugenio Culurciello, Purdue University 
• Joni Dambre, Ghent University 
• Andrew Ng or Bryan Catanzaro, Baidu Research 
• Pradeep Dubey, Intel Corporation
• Pete Warden, Google
• Olivier Temam, Google
• James E Smith, University of Wisconsin 
• Dino Sejdinovic, Dejan Vukobratovic, Dusan Jakovetic, Dragana Bajovic, University of Oxford

Introduction

With the recent success of Deep Learning and related techniques, we are beginning to see new specialized hardware or extensions to existing architectures dedicated for making training and inference computations faster or energy efficient or both. These technologies use either traditional CMOS technology on conventional von-Neumann architectures such as CPUs or accelerators such as DSPs, GPUs, FPGAs, and ASICs or other novel and exotic technologies in research phase such as  Memristors, Quantum Chips,  and Optical/Photonics. The overarching goal being to address a specific trade-off in mapping machine learning algorithms in general and deep learning in particular, to a specific underlying hardware technology.

Conversely, there has been quite an effort on the empirical side at devising deep network architectures for efficient implementation on low complexity hardware via low-rank tensor factorizations, structured matrix approximations, lower bit-depth like binary coefficients, compression and pruning to name a few approaches. This also has implications on leveraging appropriate hardware technology for inferencing primarily with energy and latency as the primary design goals. 

These efforts are finding some traction in the signal processing and sparse/compressive sensing community to map the first layers of sensing hardware with the first layers of models such as deep networks. This approach has the potential of changing the way  sensing hardware, image reconstruction, signal processing and image understanding will be performed in the future.

This workshop aims to tie these seemingly disparate themes of co-design, architecture, algorithms and signal processing and bring together researchers at the interface of machine learning, hardware implementation, sensing, physics and biology for discussing the state of the art and the state of the possible. 

The goals of the workshop are

• To present how machine learning computations and algorithms are mapped and co-designed with new hardware technologies and architectures
• To stimulate discussions on how machine learning algorithms can be co-designed or co-optimized with the underlying hardware technology to best take advantage of the synergy
• To evaluate the different trade-offs in accuracy, computational complexity, hardware cost, energy efficiency and application throughput currently investigated in these approaches
• To understand how data acquisition frameworks may be transformed to better interface with machine Learning algorithms
• To evaluate the constraints put forth on recent deep learning architectures so as to reduce redundancy and enable a simpler mapping between computing hardware and models.
• To enable a wider discussion on how Machine Learning algorithms and their primitives may provide a path toward exotic technology insertion in industrial roadmaps.

Besides the presentations made by the plenary speakers, there will be a poster session, lightning talks selected from the posters and a roundtable at the conclusion of the workshop. The workshop will be taped and presentations slides will be made available online. A white paper describing the talks and the discussions that went on during the workshop will be made available after the meeting.

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