When we talk about compressive sensing implementations, we seldomly talk about reconstruction solvers. Back in July of last year, Chris Studer was in town and did a presentation at this meeting organized by Patricia Desgreys and Laurent Daudet entitled "Acquisition/Echantillonnage comprimé : quelles réalisations/applications pratiques ?". There, he said some interesting things about empirical knowledge and reconstruction solvers and I am still trying to get a more official answer from him on that count. Anyway, in the meantime, he also detailed how they built in VLSI an instance of the FISTA reconstruction solver for quantized compressive measurements. In particular, he talked about the different simplification in the hardware implementation of ASSD in VLSI.
Here is what he had to say about this:
Hi Igor,
...I attached the slides. They are essentially about a paper we wrote a year ago:
In Section IV-A3, we mention this linear approximation. Note that right below, in Section IV-D3, we use another approximation, which replaces complex-valued shrinkage with real-valued shrinkage instead. The same section (Section IV-A) contains two other tricks tthat reduce hardware complexity....
Best, Chris
Here is this very interesting paper: VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter by David Bellasi, Luca Bettini, Christian Benkeser, Thomas Burger, Qiuting Huang, and Christoph Studer,
One of the key tasks in cognitive radio and communications intelligence is to detect active bands in the radio-frequency (RF) spectrum. In order to perform spectral activity detection in wideband RF signals, expensive and energy-inefficient high-rate analog-to-digital converters (ADCs) in combination with sophisticated digital detection circuitry are typically used. In many practical situations, however, the RF spectrum is sparsely populated, i.e., only a few frequency bands are active at a time. This property enables the design of so-called analog-to-information (A2I) converters, which are capable of acquiring and directly extracting the spectral activity information at low cost and low power by means of compressive sensing (CS). In this paper, we present the first very-large-scale integration (VLSI) design of a monolithic wideband CS-based A2I converter that includes a signal acquisition stage capable of acquiring RF signals having large bandwidths and a high-throughput spectral activity detection unit. Low-cost wideband signal acquisition is obtained via CS-based randomized temporal subsampling in combination with a 4-bit flash ADC. High-throughput spectrum activity detection from the coarsely quantized and compressive measurements is achieved by means of a massively-parallel VLSI design of a novel accelerated sparse spectrum dequantization (ASSD) algorithm. The resulting monolithic A2I converter is designed in 28 nm CMOS, acquires RF signals up to 6 GS/s, and the on-chip ASSD unit detects the active RF bands at a rate 30 × below real-time.
Let us note that generally, FPGA and related implementation focus on greedy solvers as can be shown in these two recent other papers:
Reconfigurable FPGA/GPU-Based Architecture of Block Compressive Sampling Matching Pursuit Algorithm , Amin Jarrah, Mohsin M. Jamali
The signals in reality are sparse signal where a few numbers of samples are non-zero. So, a compression technique must be applied to reduce the overhead of processing, storing, and transmission. Blocking compressive sampling matching pursuit (BCoSaMP) algorithm is a recursive algorithm which provides an accurate reconstruction of sparse signal from a small number of noisy samples. It doesn't assume that the noise is Gaussian or bounded but it uses information about the noise magnitude for stopping criterion. However, BCoSaMP is a computationally intensive algorithm. So, BCoSaMP algorithm has been implemented on both field-programmable gate array (FPGA) and graphic processing units (GPU) by exploiting parallel and pipelining approaches. A new software tool called radar signal processing tool (RSPT) is also presented. It allows the designer to auto-generate fully optimized VHDL representation of BCoSaMP by specifying many user input parameters through graphical user interface (GUI). Moreover, it provides the designer a feedback on various performance parameters. This offer the designer the ability to make any adjustments to the BCoSaMP component until gets the desired performance of the overall system-on-chip (SoC). Our simulation results indicate that the achieved speed-up of FPGA and GPU over the sequential one is improved by up to 14 and 10.7, respectively.
FPGA-based matrix inversion using an iterative Chebyshev-type method in the context of compressed sensing by Rico-Aniles, H.D. ; INAOE, Tonantzintla, Mexico ; Ramirez-Cortes, J.M. ; de Jesus Rangel-Magdaleno, J.
Compressed sensing is a recently proposed technique aiming to acquire a signal with sparse or compressible representation in some domain, using a number of samples under the limit established by the Nyquist theorem. The challenge is to recover the sensed signal solving an underdetermined linear system. Several techniques can be used for that purpose, such as l1 minimization, Greedy and combinatorial algorithms. Greedy algorithms have been found to be more suitable in hardware solutions, however they rely on efficient matrix inversion techniques in order to solve the underdetermined linear systems involved. In this paper, a novel and efficient FPGA architecture to find a matrix inversion is presented. The architecture is based on an iterative Chebyshev-type method, and it was developed in a Xilinx Spartan-6 XC6SLX45 FPGA. Preliminary results show a high accuracy with an error of 0.0001 in average.
Read More: http://www.worldscientific.com/doi/abs/10.1142/S0218126615500553
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